The present invention pertains to fabrication of integrated circuits and more particularly to systems and methods for improving fabrication yields.
Silicon based integrated circuit technology, which has evolved into sub-micron line widths, is now able to produce chips containing millions of circuit elements. The process is extremely complex, requiring a large number of process steps to produce multi-level patterns of semiconductor, metals, and insulator types of materials. The circuits are interconnected by metal lines created in multilevel geometries through a large number of very small via holes. Every process step produces three-dimensional statistical variations in the geometry and the materials properties of the final configuration. Such statistical variations, which include systematic and/or random defects, can result in both yield and performance degradation of the product. Yield and performance detractors can be found to vary across a chip, across the wafer and from wafer to wafer.
The initial design simulations for an integrated circuit chip, along with expert knowledge of the process capabilities generate a standard cell library that defines the standard device logic, memory and analog unit cells, and the design rules that define the limits and the desired dimensions of the multi-layer film and active device structures. This information is used to generate a mask set for the production of an integrated circuit product. A set of manufacturing process specifications is also generated which describes in detail the multitude of processes associated with each mask level. The mask generated for each process level defines the two dimensions parallel to the Si substrate, i.e. the planar dimensions of each processed layer. The manufacturing process specifications then determine the materials and their properties as well as the third dimension normal to the Si substrate, e.g. diffusion depths, metal thickness, and the thickness of thermally grown and deposited oxides.
For a new chip design there may be a number of iterations before an acceptable product process is defined for stable production. These iterations can include both changes to the mask set and the manufacturing specifications. The classic s-shaped xe2x80x9clearning curvexe2x80x9d is a generally accepted concept that models the manufacturing cycle for the release of such high technology type products. The initial flat section of the curve represents the initial trials of the design and process, and generally is considered to represent essentially a very low and inconsistent yield output regime. In this initial stage, some changes to the manufacturing process specifications can be made in order to stabilize the process well enough to obtain a finite but consistent yield result. The so called xe2x80x9cramp up,xe2x80x9d section of the manufacturing cycle is the section where yield of the product is consistent and is increasing rapidly. The end of the xe2x80x9clearning curvexe2x80x9d is relatively flat where the product yield is flat and stable. At this stage, the cost of the product is essentially determined by the yield, because all the manufacturing costs are relatively fixed. It is well known that the manufacturing cost of the first two sections of this learning cycle are extremely high because of the amortized cost of multi-billion dollar manufacturing facilities, as well as the cost of highly skilled personnel. Thus, a profit greater than zero must be realized at some point of the xe2x80x9cramp upxe2x80x9d cycle, and the projected business profit generally occurs at the beginning of the fixed yield cycle.
For the past thirty years, the integrated circuit technology has been increasing the density of circuits at an exponential rate. This has been accomplished by decreasing the characteristic xe2x80x9cline widthxe2x80x9d to sub-micron dimensions. Because of this, the economic requirements for the introduction of new products, as well as the maintenance of existing products, have now reached a level of great concern, because they represent very significant cost factors for the industry.
In general, the initial design phases of integrated circuits are optimized with respect to yield and performance factors through the use of elaborate simulation programs rather than through extensive process variations. The driving force for the use of simulation programs rather than the use of process variations is the much higher relative cost to manipulate the process steps.
The prior art has addressed this problem through the creation of process monitoring circuits that are incorporated within the product chip and utilize the scribe line area, (or the area between the bonding pads) within the chip reticle. Such test configurations are commonly referred to as a xe2x80x9cScribe Line Monitorxe2x80x9d (SLM). Early versions of such monitors attempted to extrapolate AC behavior through DC tests made on the test configurations through the use of simulation models. The more recent art has developed AC test methods using internal circuits within the SLM, e.g. ring oscillators and multiplexing functions that can generate limited performance and yield tests of the representative elements. In these cases it is found that the density of circuits in the SLM are not adequate to represent the behavior of a large assembly of dense circuits found on the product chip because of certain optical effects of the masks combined with the photolithography process. U.S. Pat. No. 5,703,381, Iwasa, et al., attempted to alleviate this problem by making connections to test transistors that were shared within the product configuration. Other SLM designs included circuits that contain some combinations of line lengths and via holes, chosen to represent some worst case situations that affect circuit delays. Some designs include a number of inverter gates in series for the purpose of measuring the average switching time of the logic elements. U.S. Pat. No. (6,124,143), Sugasawara, has also included representations of lines and via holes on more than one level.
Integrated circuit chips all undergo an extensive test procedure at the wafer level. Such product testers, which are extremely expensive, are designed primarily to test for functionality. Only the nominal performance of the chip can be measured using these results since the probe contact configuration, as well as the limiting capability of the measuring circuits, prevent an accurate measurement of nanosecond switching speeds that can occur during the normal operation the chip.
Elegant simulation programs have also been written in an attempt to correlate classes of observed defects with the design rules and the process steps in order to provide statistically based yield models for integrated circuit products. For example, attempts have been made to predict the yield distributions in a chip, given the data from the mask set. Although these programs have contributed to the knowledge base of the integrated circuit technologies, it has been difficult for such programs to have a direct effect on the yield and performance of a new or established product. This is because it is extremely difficult for a program to represent a class of integrated circuit products when there is an extremely wide variation in the resulting designs. A case in point is the variation in large assemblies of random logic with respect to the distribution of (multi-level) line lengths, shapes, and via holes in the interconnection scheme of a particular design. It is therefore difficult for such simulation models to take into account this unpredictable variability. One concludes that the art, with respect to simulation programs, has been useful in the creation of the initial product design, but has not proven to be very effective at optimizing the learning curve or enhancing the performance of the original design.
A number of attempts to predict yields instead of conducting unsatisfactory after the fact analysis have been made with varying degrees of success. Thus, there is a need for an improved system and method for integrated circuit product yield prediction.
The invention is a characterization vehicle, comprising at least one combinatorial circuit element, and a control circuit that controls the combinatorial circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial circuit element. An output mechanism stores an output pattern that is output by the combinatorial circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial circuit element.